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ltc2630 1 2630fd block diagram features applications description single 12-/10-/8-bit rail-to- rail dacs with integrated reference in sc70 the ltc ? 2630 is a family of 12-, 10-, and 8-bit voltage- output dacs with an integrated, high-accuracy, low-drift reference in a 6-lead sc70 package. it has a rail-to-rail output buffer and is guaranteed monotonic. the ltc2630-l has a full-scale output of 2.5v, and operates from a single 2.7v to 5.5v supply. the ltc2630-h has a full-scale output of 4.096v, and operates from a 4.5v to 5.5v supply. each dac can also operate in supply as reference mode, which sets the full-scale output to the supply voltage. the parts use a simple spi/microwire? compatible 3-wire serial interface which operates at clock rates up to 50mhz. the ltc2630 incorporates a power-on reset circuit. op- tions are available for reset to zero or reset to midscale after power-up. integral nonlinearity (ltc2630a-lz12) integrated precision reference 2.5v full scale 10ppm/c (ltc2630-l) 4.096v full scale 10ppm/c (ltc2630-h) maximum inl error: 1 lsb (ltc2630a-12) low noise: 0.7mv p-p , 0.1hz to 200khz guaranteed monotonic over temperature selectable internal reference or supply as reference 2.7v to 5.5v supply range (ltc2630-l) low power operation: 180a at 3v power down to 1.8a maximum (c and i grades) power-on reset to zero or midscale options spi serial interface double-buffered data latches tiny 6-lead sc70 package mobile communications process control and industrial automation automatic test equipment portable equipment automotive dac register resistor divider internal reference input register 24-bit shift register dac v out control decode logic cs/ld v cc gnd dacref 2630 bd sck sdi , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 5859606, 6891433 and 6937178. code 0 inl (lsb) 0 0.5 4095 2630 ta03 C0.5 C1.0 1024 2048 3072 1.0 v cc = 3v v fs = 2.5v
ltc2630 2 2630fd cs/ld 1 sck 2 sdi 3 6 v out 5 gnd 4 v cc top view sc6 package 6-lead plastic sc70 t jmax = 150? (note 6), cs scs cc cc cc c cc c cc c s cc s c c c c sc s s s s s scc c scsc cccc cc cc cc s c cc
ltc2630 3 2630fd product selection guide part number part marking* v fs with internal reference power-on reset to code resolution v cc maximum inl ltc2630a-lm12 ltc2630a-lz12 ltc2630a-hm12 ltc2630a-hz12 lczb lcsb lcwr lczc 2.5v ? (4095/4096) 2.5v ? (4095/4096) 4.096v ? (4095/4096) 4.096v ? (4095/4096) mid-scale zero mid-scale zero 12-bit 12-bit 12-bit 12-bit 2.7vC5.5v 2.7vC5.5v 4.5vC5.5v 4.5vC5.5v 1lsb 1lsb 1lsb 1lsb ltc2630-lm12 ltc2630-lm10 ltc2630-lm8 lczb lczf lcyw 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale 12-bit 10-bit 8-bit 2.7vC5.5v 2.7vC5.5v 2.7vC5.5v 2lsb 1lsb 0.5lsb ltc2630-lz12 ltc2630-lz10 ltc2630-lz8 lcsb lczd lcyv 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) zero zero zero 12-bit 10-bit 8-bit 2.7vC5.5v 2.7vC5.5v 2.7vC5.5v 2lsb 1lsb 0.5lsb ltc2630-hm12 ltc2630-hm10 ltc2630-hm8 lcwr lczh lcyy 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale 12-bit 10-bit 8-bit 4.5vC5.5v 4.5vC5.5v 4.5vC5.5v 2lsb 1lsb 0.5lsb ltc2630-hz12 ltc2630-hz10 ltc2630-hz8 lczc lczg lcyx 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) zero zero zero 12-bit 10-bit 8-bit 4.5vC5.5v 4.5vC5.5v 4.5vC5.5v 2lsb 1lsb 0.5lsb *the temperature grade is identi? ed by a label on the shipping container.
ltc2630 4 2630fd electrical characteristics symbol par ameter conditions ltc2630-8 ltc2630-10 ltc2630-12 ltc2630a-12 units min typ max min typ max min typ max min typ max dc performance resolution 8 10 12 12 bits monotonicity v cc = 3v, internal ref. (note 4) 8 10 12 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 4) 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 4) 0.05 0.5 0.2 1 1 2 0.5 1 lsb zse zero scale error v cc = 3v, internal ref., code = 0 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 5) 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coef? cient v cc = 3v, internal ref. (note 5) 10 10 10 10 v/c fse full scale error v cc = 3v, internal ref. 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %fsr v fstc full scale voltage temperature coef? cient v cc = 3v, internal ref. (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation internal ref., midscale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v 10%, C10ma i out 10ma 0.008 0.008 0.016 0.016 0.03 0.03 0.064 0.064 0.13 0.13 0.256 0.256 0.13 0.13 0.256 0.256 lsb/ma lsb/ma r out dc output impedance internal ref., midscale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v 10%, C10ma i out 10ma 0.08 0.08 0.156 0.156 0.08 0.08 0.156 0.156 0.08 0.08 0.156 0.156 0.08 0.08 0.156 0.156 the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2630-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2630a-lm12/-lz12 (v fs = 2.5v) symbol par ameter conditions min typ max units v out dac output span supply as reference internal reference 0v to v cc 0v to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero scale; v out shorted to v cc full scale; v out shorted to gnd 27 C28 50 C50 ma ma power supply v cc power supply voltage for speci? ed performance 2.7 5.5 v i cc supply current (note 7) v cc = 3v, supply as reference v cc = 3v, internal reference v cc = 5v, supply as reference v cc = 5v, internal reference 160 180 180 190 220 240 250 260 a a a a i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade 0.36 0.36 1.8 5 a a digital i/o v ih digital input high voltage v cc = 3.6v to 5.5v v cc = 2.7v to 3.6v 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v 0.8 0.6 v v i lk digital input leakage v in = gnd to v cc 1 a c in digital input capacitance (note 8) 2.5 pf
ltc2630 5 2630fd electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2630-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2630a-lm12/-lz12 (v fs = 2.5v) symbol parameter conditions min typ max units ac performance t s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.2 3.9 4.4 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at midscale transition 2 nv?s e n output voltage noise density at f = 1khz, supply as reference at f = 10khz, supply as reference at f = 1khz, internal reference at f = 10khz, internal reference 140 130 160 150 nv/hz nv/hz nv/hz nv/hz output voltage noise 0.1hz to 10hz, supply as reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, supply as reference 0.1hz to 200khz, internal reference 20 20 650 700 v p-p v p-p v p-p v p-p symbol parameter conditions min typ max units t 1 sdi valid to sck setup 4ns t 2 sdi valid to sck hold 4ns t 3 sck high time 9ns t 4 sck low time 9ns t 5 cs /ld pulse width 10 ns t 6 sck high to cs /ld high 7ns t 7 cs /ld low to sck high 7ns t 10 cs /ld high to sck positive edge 7ns sck frequency 50% duty cycle 50 mhz timing characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v. (see figure 1) (note 8). ltc2630-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2630a-lm12/-lz12 (v fs = 2.5v)
ltc2630 6 2630fd electrical characteristics symbol par ameter conditions ltc2630-8 ltc2630-10 ltc2630-12 ltc2630a-12 units min typ max min typ max min typ max min typ max dc performance resolution 8 10 12 12 bits monotonicity v cc = 5v, internal ref. (note 4) 8 10 12 12 bits dnl differential nonlinearity v cc = 5v, internal ref. (note 4) 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 5v, internal ref. (note 4) 0.05 0.5 0.2 1 1 2 0.5 1 lsb zse zero scale error v cc = 5v, internal ref., code = 0 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal ref. (note 5) 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coef? cient v cc = 5v, internal ref. (note 5) 10 10 10 10 mv/c fse full scale error v cc = 5v, internal ref. 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %fsr v fstc full scale voltage temperature coef? cient v cc = 5v, internal ref. (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation v cc = 5v 10%, internal ref., midscale, C10ma i out 10ma 0.006 0.01 0.025 0.04 0.10 0.16 0.10 0.16 lsb/ ma r out dc output impedance v cc = 5v 10%, internal ref., midscale, C10ma i out 10ma 0.1 0.156 0.1 0.156 0.1 0.156 0.1 0.156 the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2630-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2630a-hm12/-hz12 (v fs = 4.096v) symbol par ameter conditions min typ max units v out dac output span supply as reference internal reference 0v to v cc 0v to 4.096 v v psr power supply rejection v cc = 5v 10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero scale; v out shorted to v cc full scale; v out shorted to gnd 27 C28 50 C50 ma ma power supply v cc power supply voltage for speci? ed performance 4.5 5.5 v i cc supply current (note 7) v cc = 5v, supply as reference v cc = 5v, internal reference 180 200 260 280 a a i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade 0.36 0.36 1.8 5 a a digital i/o v ih digital input high voltage 2.4 v v il digital input low voltage 0.8 v i lk digital input leakage v in = gnd to v cc 1 a c in digital input capacitance (note 8) 2.5 pf
ltc2630 7 2630fd electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2630-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2630a-hm12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units ac performance t s settling time v cc = 5v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.7 4.4 4.8 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at midscale transition 2.4 nv?s e n output voltage noise density at f = 1khz, supply as reference at f = 10khz, supply as reference at f = 1khz, internal reference at f = 10khz, internal reference 140 130 210 200 nv/hz nv/hz nv/hz nv/hz output voltage noise 0.1hz to 10hz, supply as reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, supply as reference 0.1hz to 200khz, internal reference 20 20 650 750 v p-p v p-p v p-p v p-p note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. note 4: linearity and monotonicity are de? ned from code k l to code 2 n C1, where n is the resolution and k l is given by k l = 0.016 ? (2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is de? ned from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is de? ned from code 16 to code 4,095. note 5: inferred from measurement at code 16 (ltc2630-12), code 4 (ltc2630-10) or code 1 (ltc2630-8). note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: digital inputs at 0v or v cc . note 8: guaranteed by design and not production tested. note 9: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd. note 10: temperature coef? cient is calculated by dividing the maximum change in output voltage by the speci? ed temperature range. timing characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v. (see figure 1) (note 8). ltc2630-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2630a-hm12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units t 1 sdi valid to sck setup 4ns t 2 sdi valid to sck hold 4ns t 3 sck high time 9ns t 4 sck low time 9ns t 5 cs /ld pulse width 10 ns t 6 sck high to cs /ld high 7ns t 7 cs /ld low to sck high 7ns t 10 cs /ld high to sck positive edge 7ns sck frequency 50% duty cycle 50 mhz
ltc2630 8 2630fd typical performance characteristics inl vs temperature dnl vs temperature full-scale output voltage vs temperature ltc2630-lm12/-lz12 (v fs = 2.5v) integral nonlinearity (inl) code 0 inl (lsb) 0 0.5 4095 2630 g01 C0.5 C1.0 1024 2048 3072 1.0 v cc = 3v differential nonlinearity (dnl) code 0 dnl (lsb) 0 0.5 4095 2630 g02 C0.5 C1.0 1024 v cc = 3v 2048 3072 1.0 temperature (c) C50 C25 25 75 125 inl (lsb) 0 0.5 150 2630 g03 C0.5 C1.0 0 50 100 1.0 v cc = 3v inl (pos) inl (neg) temperature (c) C50 C25 25 75 125 dnl (lsb) 0 0.5 150 2630 g04 C0.5 C1.0 0 50 100 1.0 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 C25 25 75 125 fs output voltage (v) 2.50 2.51 150 2630 g05 2.49 2.48 0 50 100 2.52 v cc = 3v 2s/div 2630 g06 v out 1lsb/div 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events cs /ld 2v/div 3.6s settling to 1lsb settling to 1lsb 2s/div 2630 g07 v out 1lsb/div 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events cs/ld 2v/div 4.4s
ltc2630 9 2630fd temperature (c) C50 C25 25 75 125 fs output voltage (v) 4.095 4.105 150 2630 g12 4.085 4.075 0 50 100 4.115 v cc = 5v 2s/div 2630 g13 v out 1lsb/div 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 100pf average of 256 events cs /ld 2v/div 4.0s settling to 1lsb 2s/div 2630 g14 v out 1lsb/div cs /ld 2v/div 4.8s 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 100pf average of 256 events settling to 1lsb typical performance characteristics inl vs temperature dnl vs temperature full-scale output voltage vs temperature ltc2630-hm12/-hz12 (v fs = 4.096v) integral nonlinearity (inl) differential nonlinearity (dnl) code 0 dnl (lsb) 0 0.5 4095 2630 g09 C0.5 C1.0 1024 2048 3072 1.0 v cc = 5v code 0 inl (lsb) 0 0.5 4095 2630 g08 C0.5 C1.0 1024 2048 3072 1.0 v cc = 5v temperature (c) C50 C25 25 75 125 inl (lsb) 0 0.5 150 2630 g10 C0.5 C1.0 0 50 100 1.0 v cc = 5v inl (pos) inl (neg) temperature (c) C50 C25 25 75 125 dnl (lsb) 0 0.5 150 2630 g11 C0.5 C1.0 0 50 100 1.0 v cc = 5v dnl (pos) dnl (neg)
ltc2630 10 2630fd temperature (c) C50 C25 0 25 50 75 100 125 150 offset error (mv) 0 1 2 2630 g21 C1 C2 C3 3 i out (ma) C30 C20 C10 0 10 20 30 v out (mv) 0 2 4 6 8 2630 g19 C6 C4 C2 C8 C10 10 internal ref. code = midscale v cc = 5v (ltc2630-h) v cc = 5v (ltc2630-l) v cc = 3v (ltc2630-l) typical performance characteristics ltc2630-10 ltc2630-8 ltc2630 integral nonlinearity (inl) differential nonlinearity (dnl) integral nonlinearity (inl) code 0 inl (lsb) 0 0.5 255 2630 g17 C0.5 C1.0 64 128 192 1.0 v cc = 3v v fs = 2.5v code 0 dnl (lsb) 0 0.5 1023 2630 g16 C0.5 C1.0 256 512 768 1.0 v cc = 5v v fs = 4.096v differential nonlinearity (dnl) code 0 dnl (lsb) 0 0.25 255 2630 g18 C0.25 C0.50 64 128 192 0.50 v cc = 3v v fs = 2.5v code 0 inl (lsb) 0 0.5 1023 2630 g15 C0.5 C1.0 256 512 768 1.0 v cc = 5v v fs = 4.096v i out (ma) C30 C20 C10 0 10 20 30 $ v out (v) C0.05 0 0.05 0.10 0.15 2630 g20 C0.20 C0.15 C0.10 0.20 internal ref. code = midscale v cc = 5v (ltc2630-h) v cc = 5v (ltc2630-l) v cc = 3v (ltc2630-l) offset error vs temperature current limiting load regulation
ltc2630 11 2630fd 2s/div 0.5v/div 2630 g22 v fs = v cc = 5v 1/4 scale to 3/4 scale typical performance characteristics ltc2630 large-signal response i out (ma) 012345678910 v out (v) 2.5 2.0 3.5 3.0 4.0 2630 g25 1.5 1.0 0.5 0 5.0 4.5 5v sourcing 3v (ltc2630-l) sourcing 3v (ltc2630-l) sinking 5v sinking headroom at rails vs output current 0.1hz to 10hz voltage noise logic voltage (v) 012345 i cc (ma) 0.4 0.6 0.8 2630 g29 0.2 0 1.0 v cc = 5v v cc = 3v (ltc2630-l) sweep sck, sdi, cs /ld between 0v and v cc supply current vs logic voltage 1s/div 10v/div 2630 g27 v cc = 4v, v fs = 2.5v code = midscale noise voltage vs frequency 2s/div ltc2630-h12, v cc = 5v: 2.4nv-s typ ltc2630-l12, v cc = 3v: 2.0nv-s typ v out 5mv/div 2630 g23 cs/ld 5v/div internal ref midscale-glitch impulse power-on reset glitch 200s/div v cc 2v/div 2630 g24 ltc2630-l v out 2mv/div zero-scale frequency (hz) 100 noise voltage (nv/ hz) 200 300 1m 2630 g26 100 0 1k 10k 100k 500 400 code = midscale ltc2630-h (v cc = 5v) ltc2630-l (v cc = 4v) exiting power-down to midscale 4s/div 2630 g28 ltc2630-h cs /ld 2v/div v out 0.5v/div
ltc2630 12 2630fd block diagram pin functions cs /ld (pin 1): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the speci? ed command (see table 1) is executed. sck (pin 2): serial interface clock input. cmos and ttl compatible. sdi (pin 3): serial interface data input. data on sdi is clocked into the dac on the rising edge of sck. the ltc2630 accepts input word lengths of either 24 or 32 bits. v cc (pin 4): supply voltage input. 2.7v v cc 5.5v (ltc2630-l) or 4.5v v cc 5.5v (ltc2630-h). also used as the reference input when the part is programmed to operate in supply as reference mode. bypass to gnd with a 0.1f capacitor. gnd (pin 5): ground. v out (pin 6): dac analog voltage output. dac register resistor divider internal reference input register 24-bit shift register dac v out control decode logic cs/ld v cc gnd dacref 2630 bd sck sdi
ltc2630 13 2630fd timing diagram the ltc2630 is a family of single voltage output dacs in 6-lead sc70 packages. each dac can operate rail-to-rail referenced to the input supply, or with its full-scale volt- age set by an integrated reference. twelve combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero or midscale), and full-scale voltage (2.5v or 4.096v) are available. the ltc2630 is controlled using a 3-wire spi/microwire compatible interface. power-on reset the ltc2630-hz/-lz clear the output to zero scale when power is ? rst applied, making system initialization con- sistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2630 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mv above zero scale during power on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2630-hm/-lm provide an alternative reset, setting the output to midscale when power is ? rst applied. sdi cs/ld sck t 2 t 10 t 5 t 7 t 6 t 1 t 3 t 4 1232324 2630 f01 operation transfer function the digital-to-analog transfer function is v out(ideal) = k 2 n v ref where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5v (ltc2630-l) or 4.096v (ltc2630-h) in internal refer- ence mode, and v cc in supply as reference mode. table 1. command codes command* c3 c2 c1 c0 0 0 0 0 write to input register 0 0 0 1 update (power up) dac register 0 0 1 1 write to and update (power up) dac register 0 1 0 0 power down 0 1 1 0 select internal reference (power-on reset default) 0 1 1 1 select supply as reference (v ref = v cc ) *command codes not shown are reserved and should not be used. figure 1. serial interface timing
ltc2630 14 2630fd serial interface the cs /ld input is level triggered. when this input is taken low, it acts as a chip-select signal, enabling the sdi and sck buffers and the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded ? rst; then 4 dont-care bits; and ? nally the 16-bit data word. the data word comprises the 12-, 10- or 8-bit input code, ordered msb-to-lsb, fol- lowed by 4, 6 or 8 dont-care bits (ltc2630-12, -10 and -8 respectively; see figure 2). data can only be transferred to the device when the cs /ld signal is low, beginning on the ? rst rising edge of sck. sck may be high or low at the falling edge of cs /ld. the rising edge of cs /ld ends the data transfer and causes the device to execute the command speci? ed in the 24-bit input sequence. the complete sequence is shown in figure 3a. operation the command (c3-c0) assignments are shown in table 1. the ? rst three commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 24-bit shift register into the input register. in an update operation, the input register is copied to the dac register and converted to an analog voltage at the dac output. write to and update combines the ? rst two commands. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input sequence is 24 bits, it may optionally be extended to 32 bits to accommodate micro- processors that have a minimum word width of 16 bits (2 bytes). to use the 32-bit width, 8 dont-care bits are trans- ferred to the device ? rst, followed by the 24-bit sequence described. figure 3b shows the 32-bit sequence. 2630 f02 c3 command 4 don't-care bits msb msb msb lsb lsb lsb data (12 bits + 4 don't-care bits) c2 c1 c0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 command 4 don't-care bits data (10 bits + 6 don't-care bits) c2 c1 c0 x x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x c3 command input word (ltc2630-12) input word (ltc2630-10) input word (ltc2630-8) 4 don't-care bits data (8 bits + 8 don't-care bits) c2 c1 c0 x x x x d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x figure 2. command and data input format
ltc2630 15 2630fd the 16-bit data word is ignored for all commands that do not include a write operation. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever the dac output is not needed. when in power-down, the buffer ampli? er, bias circuit, and reference circuit are disabled and draw essentially zero current. the dac output is put into a high-impedance state, and the output pin is passively pulled to ground through a 200k resistor. input and dac register contents are not disturbed during power-down. the dac can be put into power-down mode by using command 0100. the supply current is reduced to 1.8a maximum when the dac is powered down. normal operation resumes after executing any command that includes a dac update, as shown in table 1. the dac is powered up and its voltage output is updated. normal settling is delayed while the bias, reference, and ampli? er circuits are re-enabled. the power up delay time is 18s for settling to 12 bits. reference modes for applications where an accurate external reference is not available, the ltc2630 has a user-selectable, integrated reference. the ltc2630-lm and ltc2630-lz provide a full-scale output of 2.5v. the ltc2630-hm and ltc2630- hz provide a full-scale output of 4.096v. the internal reference can be useful in applications where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110, and is the power-on default. the dac can also operate in supply as reference mode us- ing command 0111. in this mode, v cc supplies the dacs reference voltage and the supply current is reduced. voltage output the ltc2630s integrated rail-to-rail ampli? er has guaran- teed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1ma, or 50mv). see the graph headroom at rails vs. output current in the typical performance charac- teristics section. the ampli? er is stable driving capacitive loads of up to 500pf. operation
ltc2630 16 2630fd operation rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the dac cannot go below ground, it may limit for the lowest codes as shown in figure 4b. similarly, limiting can occur near full scale when using the supply as reference. if v fs = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 4. no full-scale limiting can occur if v fs is less than v cc Cfse. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2630 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2630 is no more susceptible to this effect than any other parts of this type; on the con- trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2630 is sinking large currents, this current ? ows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to con? ne digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap.
ltc2630 17 2630fd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 x x x x x x x x cs/ld sck sdi command word data word 8 dont-care bits 4 dont-care bits 2630 f03b 32-bit input word figure 3b. 32-bit load sequence ltc2630-12 sdi data word: 12-bit input code + 4 dont-care bits (shown); ltc2630-10 sdi data word: 10-bit input code + 6 dont-care bits; ltc2630-8 sdi data word: 8-bit input code + 8 dont-care bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 cs/ld sck sdi command word 4 dont-care bits data word 24-bit input word 2630 f03a figure 3a. 24-bit load sequence (minimum input word) ltc2630-12 sdi data word: 12-bit input code + 4 dont-care bits (shown); ltc2630-10 sdi data word: 10-bit input code + 6 dont-care bits; ltc2630-8 sdi data word: 8-bit input code + 8 dont-care bits operation optoisolated 4ma to 20ma process controller figure 5 shows how to use an ltc2630hz to make an optoisolated, digitally-controlled 4ma to 20ma transmit- ter. the transmitter circuitry, including optoisolation, is powered by the loop voltage which has a wide range of 5.4v to 80v. the 5v output of the lt ? 3010-5 is used to set the 4ma offset current and v out is used to digitally control the 0ma to 16ma signal current. the supply cur- rent for the regulator, dac, and op amp is well below the 4ma budget at zero scale. r s senses the total loop current, which includes the quiescent supply current and additional current through q1. note that at the maximum loop voltage of 80v, q1 will dissipate 1.6w when i out = 20ma and must have an appropriate heat sink. r offset and r gain are the closest 0.1% values to ideal for controlling a 4ma to 20ma output as the digital input varies from zero scale to full scale. alternatively, r offset can be a 365k, 1% resistor in series with a 20k trim pot and r gain can be a 75.0k, 1% resistor in series with a 5k trim pot. the optoisolators shown will limit the speed of the serial bus; the 6n139 is an alternative that will allow higher data rates.
ltc2630 18 2630fd 2630 f04 input code (b) output voltage negative offset 0v 0v 2,048 0 4,095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse operation figure 4. effects of rail-to-rail operation on a dac transfer curve (shown for 12 bits). (a) overall transfer function (b) effect of negative offset for codes near zero (c) effect of positive full-scale error for codes near full scale
ltc2630 19 2630fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. sdi sck cs/ld 2630 ta01 0.1f output 0v to 2.5v or 0v to v cc v out v cc ltc2630-lz12 gnd 2.7v to 5.5v p typical application 12-bit, 2.7v to 5.5v single supply, voltage output dac sc6 package 6-lead plastic sc70 (reference ltc dwg # 05-08-1638 rev b) 1.15 1.35 (note 4) 1.80 2.40 0.15 0.30 6 plcs (note 3) sc6 sc70 1205 rev b 1.80 2.20 (note 4) 0.65 bsc pin 1 0.80 1.00 1.00 max 0.00 0.10 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. details of the pin 1 identifier are optional, but must be located within the index area 7. eiaj package reference is eiaj sc-70 8. jedec package reference is mo-203 variation ab 2.8 bsc 0.47 max 0.65 ref recommended solder pad layout per ipc calculator 1.8 ref 1.00 ref index area (note 6) 0.10 0.18 (note 3) 0.26 0.46 gauge plane 0.15 bsc 0.10 0.40 package description
ltc2630 20 2630fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2007 lt 0808 rev d ? printed in usa related parts typical application sdi sck cs /ld 1f 1f q1 2n3440 r s 10 i out v loop 5.4v to 80v v cc v out from opto- isolated inputs ltc2630-hz 2630 ta02 3.01k 10k 1000 p f C + + ltc2054 1k r offset 374k 0.1% r gain 76.8k 0.1% opto-isolators 500 5v 10k 4n28 sdi sck cs /ld sdi sck cs /ld in out shdn sense gnd lt3010-5 figure 5. an optoisolated 4ma to 20ma process controller part number description comments ltc1660/ltc1665 octal 10-/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1663 single 10-bit v out dac in sot-23 v cc = 2.7v to 5.5v, 60a, internal reference, smbus interface ltc1664 quad 10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1669 single 10-bit v out dac in sot-23 v cc = 2.7v to 5.5v, 60a, internal reference, i 2 c interface ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611/ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2631 single 12-/10-/8-bit i 2 c v out dacs with bidirectional reference in thinsot 180a per dac, 2.7v to 5.5v supply range, bidirectional reference, rail-to-rail output, i 2 c interface ltc2640 single 12-/10-/8-bit spi v out dacs with bidirectional reference in thinsot 180a per dac, 2.7v to 5.5v supply range, bidirectional reference, rail-to-rail output, spi interface

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